The FPGA implementation of Matched Correlation Filter

被引：0
|
作者：
La, Chao [1 ]
Liu, Ming Jie [1 ]
Li, Xiao Feng [1 ]
机构：
[1] Beijing Inst Technol, Sch Mechatron Engn, Beijing 100081, Peoples R China
来源：
2011 INTERNATIONAL CONFERENCE ON ELECTRONICS, COMMUNICATIONS AND CONTROL (ICECC) | 2011年
关键词：
Matched algorithm; Correlation algorithm; Radix-4; FFT; FPGA;
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
The Matched correlation filter based on FPGA is designed for quasi real-time processing of impact acceleration signal in this paper. The design integrates match-filtering algorithm with correlation algorithm, proposing matched correlation algorithm. According to this algorithm, the design uses two Radix-4 FFT modules to complete the correlation operations, using single sine wave as matching model signal which has better correlation with impact acceleration signal. Furthermore, a re-sampling module and data integration module are added for the stability and reliability of signal processing. The filter was simulated and demonstrated by Modelsim for its good quasi real-time processing and reliability.
引用
收藏
页码：1114 / 1117
页数：4
相关论文
共 50 条
  • [1] Design and FPGA Implementation of an improved structure of digital matched filter
    Tan, Xiao-Heng
    Yang, Li-Li
    Zhang, Mao
    [J]. Chongqing Daxue Xuebao/Journal of Chongqing University, 2010, 33 (04): : 109 - 114
  • [2] A pipelined digital differential matched filter FPGA implementation & VLSI design
    Liu, KC
    Lin, WC
    Wang, CK
    [J]. PROCEEDINGS OF THE IEEE 1996 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 1996, : 75 - 78
  • [3] High-Speed Parallel Matched Filter Designing and FPGA Implementation
    ZHANG Qinglin
    [J]. Wuhan University Journal of Natural Sciences, 2010, 15 (04) : 335 - 339
  • [4] An Implementation Method of Partial Correlation Matched Filter in the CDMA Receiver
    Ding Guodong
    Fang Zhigang
    [J]. 2016 2ND IEEE INTERNATIONAL CONFERENCE ON COMPUTER AND COMMUNICATIONS (ICCC), 2016, : 2323 - 2327
  • [5] FPGA-Based Implementation of a Matched Filter for Acoustic Shooter Localization System
    Baki, Bilgehan Mirac
    Yalcin, Mustak E.
    [J]. 2023 31ST SIGNAL PROCESSING AND COMMUNICATIONS APPLICATIONS CONFERENCE, SIU, 2023,
  • [6] FPGA implementation of median filter
    Maheshwari, R
    Rao, SSSP
    Poonacha, PG
    [J]. TENTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 1997, : 523 - 524
  • [7] FPGA Implementation of Digital Filter
    Liu, Fan
    [J]. DCABES 2008 PROCEEDINGS, VOLS I AND II, 2008, : 1338 - 1341
  • [8] FPGA implementation of a median filter
    Bates, GL
    Nooshabadi, S
    [J]. IEEE TENCON'97 - IEEE REGIONAL 10 ANNUAL CONFERENCE, PROCEEDINGS, VOLS 1 AND 2: SPEECH AND IMAGE TECHNOLOGIES FOR COMPUTING AND TELECOMMUNICATIONS, 1997, : 437 - 440
  • [9] Matched filter computation on FPGA, cell and GPU
    Baker, Zachary K.
    Gokhale, Maya B.
    Tripp, Justin L.
    [J]. FCCM 2007: 15TH ANNUAL IEEE SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES, PROCEEDINGS, 2007, : 207 - +
  • [10] CIC Decimation Filter Implementation on FPGA
    Datta D.
    Dutta H.S.
    [J]. Journal of The Institution of Engineers (India): Series B, 2023, 104 (01) : 85 - 90
12345