ULTRA-LOW-POWER LOW DROP-OUT (LDO) VOLTAGE REGULATOR WITH IMPROVED POWER SUPPLY REJECTION

被引：1

作者：

Hammam, Hazem H. ^{[1
]}

Omran, Hesham A. ^{[1
]}

Ibrahim, Sameh A. ^{[1
]}

机构：

[1] Ain Shams, Dept Comm & Elect Engn, Cairo, Egypt

来源：

PROCEEDINGS OF 2021 38TH NATIONAL RADIO SCIENCE CONFERENCE (NRSC) | 2021年

关键词：

Low power; analog integrated circuits; Low drop-out regulator; Power-supply rejection; HIGH PSR; CANCELLATION; BANDWIDTH;

D O I：

10.1109/NRSC52299.2021.9509816

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Having a high-power supply rejection (PSR) over a wide range of frequencies is a very important specification for most of low-dropout voltage regulators (LDOs). A low-power LDO with 2 methods of high-frequency PSR and loop stability compensation techniques is presented in this paper. The proposed LDO achieves a high PSR over a wide frequency range with low power and small area consumption. The LDO is implemented in 65 nm CMOS technology and achieves a PSR better than 77 dB up to 30 MHz for output load currents up to 25 mA and a 4 mu F output load capacitor. The design is suitable for capacitor loaded (Capped) LDOs with a wide output load current range up to 100 mA and output load capacitor range from 1 mu F to 12 mu F. The proposed LDO consumes a no-load quiescent current of 5 mu A and an area of 400 mu m x 200 mu m.

引用

页码：177 / 185

页数：9

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