PVT Variations in Differential Flip-Flops: A Comparative Analysis

被引：0
|
作者：
Alioto, Massimo [1 ]
Palumbo, Gaetano [2 ]
Consoli, Elio [3 ]
机构：
[1] ECE Natl Univ Singapore, Singapore, Singapore
[2] Univ Catania, DIEEI, I-95124 Catania, Italy
[3] Maxim Integrated Prod, Catania, Italy
来源：
2015 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN (ECCTD) | 2015年
关键词：
DELAY-AREA DOMAIN; DESIGN;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, the impact of variations on the most representative CMOS differential flip-flops has been evaluated. The analysis explicitly considers fundamental sources of variations such as process, voltage, temperature and clock slope. For each FF topology, the variations are statistically evaluated through Monte Carlo simulations and they explicitly include the non-negligible impact of layout parasitics.
引用
收藏
页码：81 / 84
页数：4
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