Challenges and Directions for Low-Voltage SRAM

被引：50

作者：

Qazi, Masood ^{[1
]}

Sinangil, Mahmut E. ^{[1
]}

Chandrakasan, Anantha P. ^{[1
]}

机构：

[1] MIT, Microsyst Technol Labs, Cambridge, MA 02139 USA

来源：

IEEE DESIGN & TEST OF COMPUTERS | 2011年 / 28卷 / 01期

关键词：

SUBTHRESHOLD SRAM; TECHNOLOGY; DESIGN; READ; MANUFACTURABILITY; GENERATION; SCHEME; CACHE; CMOS; CELL;

D O I：

10.1109/MDT.2010.115

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Editor's note: SRAMs capable of operating at extremely low supply voltages - for example, below the transistor threshold voltage - can enable ultra-low-power battery-operated systems by allowing the logic and memory to operate at the same optimal supply voltage. This review article presents SRAM techniques including new bit cells, novel sensing schemes, and read/write assist circuits for ultra-low-power applications. © 2006 IEEE.

引用

页码：32 / 43

页数：12

共 50 条

[1] A STUDY OF LOW-VOLTAGE OPERATION SRAM
YAMAGUCHI, T
MATTHEWS, F
SATO, N
UEOKA, J
NATSUME, H
MITANI, H
[J]. NEC RESEARCH & DEVELOPMENT, 1995, 36 (01): : 64 - 71
[2] A Novel BIST Algorithm for Low-voltage SRAM
Cai, Zhikuang
Wang, Ying
Liu, Shihuan
Lv, Kai
Wang, Zixuan
[J]. 2019 IEEE INTERNATIONAL TEST CONFERENCE IN ASIA (ITC-ASIA 2019), 2019, : 133 - 138
[3] A 512 Kbit low-voltage NV-SRAM with the size of a conventional SRAM
Miwa, T
Yamada, J
Koike, H
Nakura, T
Kobayashi, S
Kasai, N
Toyoshima, H
[J]. 2001 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2001, : 129 - 132
[4] Merits of CMOS SIMOX technology for low-voltage SRAM macros
Kumagai, K
Iwaki, H
Yamada, T
Nakamura, H
Onishi, H
Matsubara, Y
Imai, K
Kurosawa, S
[J]. NEC RESEARCH & DEVELOPMENT, 1999, 40 (03): : 287 - 291
[5] A Timing-Shared Adaptive Sensing Methodology for Low-Voltage SRAM
Zhou, Yongliang
Yang, Zhen
Wei, Yiming
Lin, Xiao
Wu, Saiai
Lu, Wenjuan
Peng, Chunyu
Li, Xin
Wu, Xiulong
[J]. 2024 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS 2024, 2024,
[6] A new analytical model of SRAM cell stability in low-voltage operation
Ichikawa, T
Sasaki, M
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1996, 43 (01) : 54 - 61
[7] Challenges of partial discharge diagnostics of low-voltage cables
Cselko, Richard
Berta, Istvan
[J]. JOURNAL OF ELECTROSTATICS, 2013, 71 (03) : 558 - 563
[8] A low-voltage loadless 4N SRAM with smart hidden refresh
Huang, HY
Yen, TS
[J]. IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS, 2003, : 251 - 252
[9] Challenges of PV Integration in Low-Voltage Secondary Networks
Mohammadi, P.
Mehraeen, S.
[J]. IEEE TRANSACTIONS ON POWER DELIVERY, 2017, 32 (01) : 525 - 535
[10] Fundamental Thermal Limits on Data Retention in Low-Voltage CMOS Latches and SRAM
Rezaei, Elahe
Donato, Marco
Patterson, William R.
Zaslavsky, Alexander
Bahar, R. Iris
[J]. IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2020, 20 (03) : 488 - 497

← 1 2 3 4 5 →