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Challenges and Directions for Low-Voltage SRAM
被引:50
|
作者
:
Qazi, Masood
论文数:
0
引用数:
0
h-index:
0
机构:
MIT, Microsyst Technol Labs, Cambridge, MA 02139 USA
MIT, Microsyst Technol Labs, Cambridge, MA 02139 USA
Qazi, Masood
[
1
]
Sinangil, Mahmut E.
论文数:
0
引用数:
0
h-index:
0
机构:
MIT, Microsyst Technol Labs, Cambridge, MA 02139 USA
MIT, Microsyst Technol Labs, Cambridge, MA 02139 USA
Sinangil, Mahmut E.
[
1
]
Chandrakasan, Anantha P.
论文数:
0
引用数:
0
h-index:
0
机构:
MIT, Microsyst Technol Labs, Cambridge, MA 02139 USA
MIT, Microsyst Technol Labs, Cambridge, MA 02139 USA
Chandrakasan, Anantha P.
[
1
]
机构
:
[1]
MIT, Microsyst Technol Labs, Cambridge, MA 02139 USA
来源
:
IEEE DESIGN & TEST OF COMPUTERS
|
2011年
/ 28卷
/ 01期
关键词
:
SUBTHRESHOLD SRAM;
TECHNOLOGY;
DESIGN;
READ;
MANUFACTURABILITY;
GENERATION;
SCHEME;
CACHE;
CMOS;
CELL;
D O I
:
10.1109/MDT.2010.115
中图分类号
:
TP3 [计算技术、计算机技术];
学科分类号
:
0812 ;
摘要
:
Editor's note: SRAMs capable of operating at extremely low supply voltages - for example, below the transistor threshold voltage - can enable ultra-low-power battery-operated systems by allowing the logic and memory to operate at the same optimal supply voltage. This review article presents SRAM techniques including new bit cells, novel sensing schemes, and read/write assist circuits for ultra-low-power applications. © 2006 IEEE.
引用
收藏
页码:32 / 43
页数:12
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