Modeling architectures for VLSI implementations of fuzzy logic systems

被引:0
|
作者
Roche, B [1 ]
McGinnity, TM [1 ]
Maguire, LP [1 ]
McDaid, LJ [1 ]
机构
[1] Univ Ulster, Magee Coll, Fac Engn, Intelligent Syst Engn Lab, Derry BT48 7JL, North Ireland
关键词
D O I
10.1016/S0020-0255(98)10089-0
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
A model for predicting silicon area occupied by a fuzzy logic system implemented in VLSI is presented. The model aims to allow designers to estimate the feasibility of implementing their fuzzy logic system in hardware and should also enable the identification of core-limited or interconnect-limited designs. A set of examples showing typical results are presented. These illustrate the dominant impact of interconnect on silicon area in hardware implementations of fuzzy logic systems. (C) 1999 Elsevier Science Inc. All rights reserved.
引用
收藏
页码:1 / 9
页数:9
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