VLSI implementations of threshold logic - A comprehensive survey

被引：154

作者：

Beiu, V ^{[1
]}

Quintana, JM

Avedillo, MJ

机构：

[1] Washington State Univ, Sch Elect Engn & Comp Sci, Pullman, WA 99164 USA

[2] Univ Seville, CNM, IMSE, E-41012 Seville, Spain

来源：

IEEE TRANSACTIONS ON NEURAL NETWORKS | 2003年 / 14卷 / 05期

关键词：

integrated circuits; neural-network (NN) hardware; threshold logic; very-large-scale integration (VLSI);

D O I：

10.1109/TNN.2003.816365

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper is an in-depth review on silicon implementations of threshold logic gates that covers several decades. In this paper, we will mention early MOS threshold logic solutions and detail numerous very-large-scale integration (VLSI) implementations including capacitive (switched capacitor and floating gate with their variations), conductance/current (pseudo-nMOS and output-wired-inverters, including a plethora of solutions evolved from them), as well as many differential solutions. At the end, we will briefly mention other implementations, e.g., based on negative resistance devices and on single electron technologies.

引用

页码：1217 / 1243

页数：27

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