State-of-the-art in CMOS threshold-logic VLSI gate implementations and applications

被引:7
|
作者
Celinski, P [1 ]
Cotofana, SD [1 ]
López, JF [1 ]
Al-Sarawi, S [1 ]
Abbott, D [1 ]
机构
[1] Univ Adelaide, Dept Elect & Elect Engn, CHiPTec, Adelaide, SA 5005, Australia
来源
VLSI CIRCUITS AND SYSTEMS | 2003年 / 5117卷
关键词
threshold logic; VLSI; computer arithmetic;
D O I
10.1117/12.497792
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In recent years, there has been renewed interest in Threshold Logic (TL), mainly as a result of the development of a number of successful implementations of TL gates in CMOS. This paper presents a summary of the recent developments in TL circuit design. High-performance TL gate circuit implementations are compared, and a number of their applications in computer arithmetic operations are reviewed. It is shown that the application of TL in computer arithmetic circuit design can yield designs with significantly reduced transistor count and area while at the same time reducing circuit delay and power dissipation when compared to conventional CMOS logic.
引用
收藏
页码:53 / 64
页数:12
相关论文
共 50 条
  • [1] Low-power CMOS threshold-logic gate
    Avedillo, MJ
    Quintana, JM
    Rueda, A
    Jimenez, E
    [J]. ELECTRONICS LETTERS, 1995, 31 (25) : 2157 - 2159
  • [2] A capacitive threshold-logic gate
    Ozdemir, H
    Kepkep, A
    Pamir, B
    Leblebici, Y
    Cilingiroglu, U
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1996, 31 (08) : 1141 - 1150
  • [3] Low-cost BSA technique for threshold-logic gate based multiplier implementations
    Quintana, JM
    Avedillo, MJ
    Rueda, A
    [J]. ELECTRONICS LETTERS, 1997, 33 (12) : 1028 - 1030
  • [4] A Balanced Capacitive Threshold-Logic Gate
    Javier López-García
    José Fernández-Ramos
    Alfonso Gago-Bohórquez
    [J]. Analog Integrated Circuits and Signal Processing, 2004, 40 : 61 - 69
  • [5] A balanced capacitive threshold-logic gate
    López-García, J
    Fernández-Ramos, J
    Gago-Bohórquez, AG
    [J]. ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2004, 40 (01) : 61 - 69
  • [6] On the Design of Nanoscale CMOS Threshold-Logic Adders
    Sulieman, Mawahib Hussein
    Himat, Zakaria FadlAlmoula
    [J]. 2018 15TH INTERNATIONAL MULTI-CONFERENCE ON SYSTEMS, SIGNALS AND DEVICES (SSD), 2018, : 1037 - 1040
  • [7] Threshold-Logic Devices Consisting of Subthreshold CMOS Circuits
    Ogawa, Taichi
    Hirose, Tetsuya
    Asai, Tetsuya
    Amemiya, Yoshihito
    [J]. IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2009, E92A (02): : 436 - 442
  • [8] VLSI implementations of threshold logic - A comprehensive survey
    Beiu, V
    Quintana, JM
    Avedillo, MJ
    [J]. IEEE TRANSACTIONS ON NEURAL NETWORKS, 2003, 14 (05): : 1217 - 1243
  • [9] OTRA, its implementations and applications: a state-of-the-art review
    Abdhesh K. Singh
    Raj Senani
    Ashish Gupta
    [J]. Analog Integrated Circuits and Signal Processing, 2018, 97 : 281 - 311
  • [10] OTRA, its implementations and applications: a state-of-the-art review
    Singh, Abdhesh K.
    Senani, Raj
    Gupta, Ashish
    [J]. ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2018, 97 (02) : 281 - 311