Performance Analysis of Dual-Material Gate SOI MOSFET

被引：2

作者：

Liu, Hongxia ^{[1
]}

Kuang, Qianwei ^{[1
]}

Luan, Suzhen ^{[1
]}

Hao, Yue ^{[1
]}

机构：

[1] Xidian Univ, Sch Microelect, Xian, Peoples R China

来源：

2009 IEEE INTERNATIONAL CONFERENCE OF ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC 2009) | 2009年

基金：

中国国家自然科学基金;

关键词：

SOI MOSFET; dual material gates (DMG); high k dielectric; drain-induced barrier lowering (DIBL); short-channel effect (SCE); HIGH-K; DIELECTRICS;

D O I：

10.1109/EDSSC.2009.5394188

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, a novel device structure called dual-material gate SOI MOSFET (DMG SOI MOSFET) is proposed to restrain drain-induced barrier lowering (DIBL) and short-channel effect (SCE) for the advanced nanometer process. The analytical threshold voltage model of novel structure device is presented, and the electrical characteristics are analyzed. The DMG SOI MOSFET with high k dielectric shows better performance in suppressing DIBL and enhancing carrier transport efficiency than the conventional SOT MOSFET. The DIBL is reduced with increasing dielectric constant. The analytical threshold voltage model is in good agreement with the two-dimensional device simulator ISE.

引用

页码：63 / +

页数：2

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