Modelling of direct tunneling gate leakage current of floating-gate CMOS transistor in sub 100 nm technologies

While floating-gate MOS transistor in mixed-signal applications have been studied in the literature, little has been reported on modeling them with gate leakage current (GLC). This paper presents a simulation model for floating-gate MOS transistor in nanometer-scale technologies. The proposed model accounts for direct tunnelling GLC in sub 3 nm gate oxide thickness. The model can be used for both transient and DC simulations with any industry standard simulators. HSPICE simulations and measurements of an experimental chip using TSMC 90 nm technology were presented.