共 50 条
- [31] On-Chip Memory Technology Design Space Explorations for Mobile Deep Neural Network Accelerators PROCEEDINGS OF THE 2019 56TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2019,
- [32] Efficient Hierarchical Discretization of Off-chip Power Delivery Network Geometries for 2.5D Electrical Analysis PROCEEDINGS OF THE ELEVENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2010), 2010, : 590 - 597
- [33] Stick Buffer Cache v2: Improved Input Feature Map Cache for Reducing off-chip Memory Traffic in CNN Accelerators 2019 27TH TELECOMMUNICATIONS FORUM (TELFOR 2019), 2019, : 450 - 453
- [35] Considerations of Integrating Computing-In-Memory and Processing-In-Sensor into Convolutional Neural Network Accelerators for Low-Power Edge Devices 2019 SYMPOSIUM ON VLSI CIRCUITS, 2019, : T166 - T167
- [36] Sparse Periodic Systolic Dataflow for Lowering Latency and Power Dissipation of Convolutional Neural Network Accelerators 2022 ACM/IEEE INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, ISLPED 2022, 2022,
- [37] Approximated Prediction Strategy for Reducing Power Consumption of Convolutional Neural Network Processor PROCEEDINGS OF 29TH IEEE CONFERENCE ON COMPUTER VISION AND PATTERN RECOGNITION WORKSHOPS, (CVPRW 2016), 2016, : 870 - 876
- [38] Design Tradeoff of Internal Memory Size and Memory Access Energy in Deep Neural Network Hardware Accelerators 2018 IEEE 7TH GLOBAL CONFERENCE ON CONSUMER ELECTRONICS (GCCE 2018), 2018, : 735 - 736