Problems in PLD implementation of all-digital DLL

被引：0

作者：

Matic, Tomislav ^{[1
]}

Svedek, Tomislav ^{[1
]}

Herceg, Marijan ^{[1
]}

机构：

[1] JJ Strossmayer Univ Osijek, Fac Elect Engn, Dept Commun, Osijek, Croatia

来源：

2008 3RD INTERNATIONAL SYMPOSIUM ON COMMUNICATIONS, CONTROL AND SIGNAL PROCESSING, VOLS 1-3 | 2008年

关键词：

D O I：

10.1109/ISCCSP.2008.4537390

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

Problems encountered in the implementation of an all-digital delay-locked loop (DLL) in programmable logic devices (PLD) are presented. All parts of a DLL are only created by discrete digital elements. A digital controlled delay line (DCDL) consists of digital controlled delay elements (DCDE) realized by a number of LCELLs (basic delay elements in ALTERA's PLD). An analog charge pump (CP) and a loop filter (LF) in the proposed circuit are replaced with a 3-bit UP/DOWN/HOLD counter. The proposed DLL is implemented and tested in the ALTERA PLD chip EPM7128SLI10.

引用

页码：1107 / 1110

页数：4

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