A TCP offload accelerator for 10 Gb/s ethernet in 90-nm CMOS

被引：19

作者：

Hoskote, Y ^{[1
]}

Bloechel, BA ^{[1
]}

Dermer, GE ^{[1
]}

Erraguntla, V ^{[1
]}

Finan, D ^{[1
]}

Howard, J ^{[1
]}

Klowden, D ^{[1
]}

Narendra, SG ^{[1
]}

Ruhl, G ^{[1
]}

Tschanz, JW ^{[1
]}

Vangal, S ^{[1
]}

Veeramachaneni, V ^{[1
]}

Wilson, H ^{[1
]}

Xu, JP ^{[1
]}

Borkar, N ^{[1
]}

机构：

[1] Intel Corp, Hillsboro, OR 97124 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2003年 / 38卷 / 11期

关键词：

gigabit Ethernet; offload; packet processing; special-purpose; processor; TCP;

D O I：

10.1109/JSSC.2003.818294

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This programmable engine is designed to offload TCP inbound processing at wire speed for 10-Gb/s Ethernet, supporting 64-byte minimum packet size. This prototype chip employs a high-speed core and a specialized instruction set. It includes hardware support for dynamically reordering out-of-order packets. In a 90-nm CMOS process, the 8-mm(2) experimental chip has 460 K transistors. First silicon has been validated to be fully functional and achieves 9.64-Gb/s packet processing performance at 1.72 V and consumes 6.39 W.

引用

页码：1866 / 1875

页数：10

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