Low power 10 Gb/s serial link transmitter in 90-nm CMOS

被引：0
|
作者：
Rylyakov, A [1 ]
Rylov, S [1 ]
机构：
[1] IBM Corp, Thomas J Watson Res Ctr, Yorktown Hts, NY 10598 USA
来源：
2005 IEEE CSIC SYMPOSIUM, TECHNICAL DIGEST | 2005年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A 10Gb/s half-rate serial link differential transmitter is optimized for low power and features a 4:1 multiplexer and a 4-tap feed-forward equalizer. The chip is error-free at 10Gb/s (2(31)-1 PRBS) and 125 degrees C, driving an AC-coupled 100 Ohm differential load with a 0.9V peak-to-peak differential (ppd) signal and consuming a total of 174mW (80mA from a 1.65V supply in the output driver section and 35mA from 1.2V in the multiplexer section).
引用
收藏
页码：189 / 191
页数：3
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