Design of 3.3V 10bit current-mode folding/interpolating CMOS A/D converter with an arithmetic functionality

被引：0

作者：

Chung, JW ^{[1
]}

Yoon, KS ^{[1
]}

机构：

[1] Inha Univ, Dept Elect Engn, Nam Gu, Inchon 402751, South Korea

来源：

PROCEEDINGS OF THE SECOND IEEE ASIA PACIFIC CONFERENCE ON ASICS | 2000年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A low power 10bit current-mode folding and interpolating CMOS analog to digital converter (ADC) with arithmetic folding block is presented in this paper. A current-mode two-level folding amplifier with a high folding rate (FR) is designed not only to prevent ADC from increasing a FR excessively, but also to perform a high resolution at a single power supply of 3.3V The proposed ADC is implemented by a 0.6 mum n-well CMOS single poly/double metal process. The simulation result shows a differential nonlinearity (DNL) of +/-0.5LSB, an integral nonlinearity (INL) of +/-1.0LSB.

引用

页码：45 / 48

页数：4

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