Monolithic Three-Dimensional Integration of Carbon Nanotube FETs with Silicon CMOS

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作者
Shulaker, Max M. [1 ]
Saraswat, Krishna [1 ]
Wong, H. -S. Philip [1 ]
Mitra, Subhasish [1 ]
机构
[1] Stanford Univ, Stanford, CA 94305 USA
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TM [电工技术]; TN [电子技术、通信技术];
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0808 ; 0809 ;
摘要
We demonstrate the first VLSI-compatible approach for monolithic three-dimensional (3D) integration of carbon nanotube field effect transistors (CNFETs) with silicon CMOS for high-performance digital logic applications. Fine-grained monolithic 3D integration is demonstrated at the logic gate level, whereby individual logic gates are composed of both CNFETs and silicon FETs. Monolithic 3D integration is additionally achieved at the circuit-level, with CNFET logic gates cascaded with silicon CMOS logic gates, creating hybrid CNFET-silicon CMOS logic circuits. All the CNFET fabrication steps are VLSI-scalable and silicon CMOS compatible. CNFET fabrication is performed after the silicon CMOS processing is completed and the CNFETs directly overlap on top of the silicon FETs. This work demonstrates both the compatibility of CNFETs with silicon CMOS and the ability to achieve monolithic 3D ICs simultaneously using silicon CMOS and CNFETs.
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