Phase noise improvement in fractional-N synthesizer with 90° phase shift lock

被引：0

作者：

Park, J ^{[1
]}

Maloberti, F ^{[1
]}

机构：

[1] Univ Texas, Dept Elect Engn, Dallas, TX 75235 USA

来源：

PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I: ANALOG CIRCUITS AND SIGNAL PROCESSING | 2003年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An effective technique for phase noise improvement in a fractional-N synthesizer is described. The method requires using in a 90degrees phase shift lock a non-linear continuous-time or sampled-data block before the loop filter. Behavioral simulations on a fractional-N synthesizer incorporating different non-linear blocks and a second-order single bit sigma delta modulator show that it is possible to achieve phase noise improvements at medium frequency as good as 17 dB.

引用

页码：733 / 736

页数：4

共 50 条

[41] Fractional-N Frequency Synthesizer with Low Phase Noise and Low Power Dissipation for Intelligent Vehicle-to-Vehicle Radio Control Applications
Lai, Wen-Cheng
2020 INTERNATIONAL AUTOMATIC CONTROL CONFERENCE (CACS), 2020,
[42] A Technique for In-Band Phase Noise Reduction in Fractional-N Frequency Synthesizers
Wang, Chun-Ping
Lee, Tai-Cheng
2016 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC), 2016, : 273 - 276
[43] A new fractional-N PLL frequency synthesizer
Sumi, Y
Obote, S
Fukui, Y
Tsuda, K
Syoubu, K
JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 1997, 7 (05) : 395 - 405
[44] A generalized MASH architecture in Fractional-N synthesizer
Zhu, YH
Shao, ZB
Pang, WY
2004: 7TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUITS TECHNOLOGY, VOLS 1- 3, PROCEEDINGS, 2004, : 1512 - 1515
[45] A fractional-N PLL frequency synthesizer design
Kim, S
Kim, Y
Proceedings of the IEEE SoutheastCon 2004: EXCELLENCE IN ENGINEERING, SCIENCE, AND TECHNOLOGY, 2005, : 84 - 87
[46] A 4 GHz ΔΣ Fractional-N Frequency Synthesizer
Rami Ahola
Kari Halonen
Analog Integrated Circuits and Signal Processing, 2003, 34 : 77 - 87
[47] An Investigation of Phase Noise of a Fractional-N PLL in the Course of FMCW Chirp Generation
Ergintav, Arzu
Herzel, Frank
Kissinger, Dietmar
Ng, Herman Jalli
2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2018,
[48] A fractional-N frequency synthesizer architecture utilizing a mismatch compensated PFD/DAC structure for reduced quantization-induced phase noise
Meninger, SE
Perrott, MH
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2003, 50 (11) : 839 - 849
[49] A 4 GHz fractional-N frequency synthesizer
Ahola, R
Halonen, K
ICECS 2000: 7TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS & SYSTEMS, VOLS I AND II, 2000, : 239 - 242
[50] A 4 GHz ΔΣ fractional-N frequency synthesizer
Ahola, R
Halonen, K
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2003, 34 (02) : 77 - 87

← 1 2 3 4 5 →