A Flexible Hardware Barrier Mechanism for Many-Core Processors

被引：0

作者：

Soga, Takeshi ^{[1
]}

Sasaki, Hiroshi ^{[2
]}

Hirao, Tomoya ^{[2
]}

Kondo, Masaaki ^{[3
]}

Inoue, Koji ^{[2
]}

机构：

[1] ISIT, JST CREST, Inst Syst Informat Technol & Nanotechnol, Fukuoka, Japan

[2] Kyushu Univ, Fukuoka, Japan

[3] Univ Tokyo, Tokyo, Japan

来源：

2015 20TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC) | 2015年

关键词：

SYSTEM;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper proposes a new hardware barrier mechanism which offers the flexibility to select which cores should join the synchronization, allowing for executing multiple multi-threaded applications by dividing a many-core processor into several groups. Experimental results based on an RTL simulation show that our hardware barrier achieves a 66-fold reduction in latency over typical software based implementations, with a hardware overhead of the processor of only 1.8%. Additionally, we demonstrate that the proposed mechanism is sufficiently flexible to cover a variety of core groups with minimal hardware overhead.

引用

页码：61 / 68

页数：8

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