Design of high-speed CAVLC decoder architecture for H.264/AVC

被引：5

作者：

Oh, Myungseok ^{[1
]}

Lee, Wonjae ^{[1
]}

Jung, Yunho ^{[1
]}

Kim, Jaeseok ^{[1
]}

机构：

[1] Yonsei Univ, Dept Elect & Elect Engn, Seoul 120749, South Korea

来源：

ETRI JOURNAL | 2008年 / 30卷 / 01期

关键词：

CAVLC; VLC; entropy coding; H.264/AVC;

D O I：

10.4218/etrij.08.0207.0208

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper we propose hardware architecture for a high-speed context-adaptive variable length coding (CAVLC) decoder in H.264. In the CAVLC decoder the codeword length of the current decoding block is used to determine the next input bitstreams (valid bits). Since the computation of valid bits increases the total processing time of CAVLC, we propose two techniques to reduce processing time: one is to reduce the number of decoding steps by introducing a lookup table, and the other is to reduce cycles for calculating the valid bits. The proposed CAVLC decoder can decode 1920 x 1088 30 fps video in real time at a 30.8 MHz clock.

引用

页码：167 / 169

页数：3

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