Read and write circuit assist techniques for improving Vccmin of dense 6T SRAM cell

被引：17

作者：

Khellah, Muhammad M. ^{[1
]}

Keshavarzi, Ali ^{[1
]}

Somasekhar, Dinesh ^{[1
]}

Karnik, Tanay ^{[1
]}

De, Vivek ^{[1
]}

机构：

[1] Intel Corp, Circuits Res Lab, Hillsboro, OR 97124 USA

来源：

2008 IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUIT DESIGN AND TECHNOLOGY, PROCEEDINGS | 2008年

关键词：

D O I：

10.1109/ICICDT.2008.4567275

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We review circuit techniques aimed at improving read and write stability of the smallest 6T SRAM cell typically used in microprocessor's Last Level cache (LLC). We qualitatively compare three main approaches and give a designer's perspective on the pros and cons of the different schemes.

引用

页码：185 / 188

页数：4

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