Optimal design of a CMOS op-amp via geometric programming

被引:326
|
作者
Hershenson, MD [1 ]
Boyd, SP
Lee, TH
机构
[1] Barcelona Design Inc, Sunnyvale, CA 94086 USA
[2] Stanford Univ, Dept Elect Engn, Stanford, CA 94305 USA
关键词
circuit optimization; CMOS analog integrated circuits; design automation; geometric programming; mixed analog-digital integrated circuits; operational amplifiers;
D O I
10.1109/43.905671
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
We describe a new method for determining component values and transistor dimensions for CMOS operational amplifiers (op-amps). We observe that a wide variety of design objectives and constraints have a special form, i.e., they are posynomial functions of the design variables. As a result, the amplifier design problem can be expressed as a special form of optimization problem called geometric programming, for which very efficient global optimization methods have been developed. As a consequence we can efficiently determine globally optimal amplifier designs or globally optimal tradeoffs among competing performance measures such as power, open-loop gain, and bandwidth. Our method, therefore, yields completely automated sizing of (globally) optimal CMOS amplifiers, directly from specifications. In this paper, we apply this method to a specific widely used operational amplifier architecture, showing in detail how to formulate the design problem as a geometric program. We compute globally optimal tradeoff curves relating performance measures such as power dissipation, unity-gain bandwidth, and open-loop gain. We show how the method can be used to size robust designs, i.e., designs guaranteed to meet the specifications for a variety of process conditions and parameters.
引用
收藏
页码:1 / 21
页数:21
相关论文
共 50 条
  • [21] Design of a 0.5 V op-amp based on CMOS inverter using floating voltage sources
    Wang, Jun
    Lee, Tuck-Yang
    Kim, Dong-Gyou
    Matsuoka, Toshimasa
    Taniguchi, Kenji
    [J]. IEICE TRANSACTIONS ON ELECTRONICS, 2008, E91C (08) : 1375 - 1378
  • [22] OP-AMP PRE-AMP
    HEDGELAN.DR
    [J]. WIRELESS WORLD, 1972, 78 (1446): : 575 - 575
  • [23] Noise analysis in a 0.8 V forward body-bias CMOS op-amp design
    Zhang, C
    Srivastava, A
    Ajmera, PK
    [J]. FLUCTUATION AND NOISE LETTERS, 2004, 4 (02): : L403 - L412
  • [24] A high-speed CMOS Op-Amp design technique using negative miller capacitance
    Shem-Tov, B
    Kozak, M
    Friedman, EG
    [J]. ICECS 2004: 11TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, 2004, : 623 - 626
  • [25] Op-amp based CMOS field-programmable analogue array
    Looby, CA
    Lyden, C
    [J]. IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, 2000, 147 (02): : 93 - 99
  • [26] Telescopic op-amp optimization for mdac circuit design
    Dendouga A.
    Oussalah S.
    [J]. Electronics, 2016, 20 (02) : 55 - 61
  • [27] Design and Performance Analysis of a Digitally Programmable Op-Amp
    Zaidi, Muhaned
    Grout, Ian
    A'ain, Abu Khari
    [J]. 2018 INTERNATIONAL CONFERENCE ON INTELLIGENT AND ADVANCED SYSTEM (ICIAS 2018) / WORLD ENGINEERING, SCIENCE & TECHNOLOGY CONGRESS (ESTCON), 2018,
  • [28] A 1.5-V high drive capability CMOS op-amp
    Palmisano, G
    Palumbo, G
    Salerno, R
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1999, 34 (02) : 248 - 252
  • [29] Demystifying single-supply op-amp design
    Kitchin, C
    [J]. EDN, 2002, 47 (06) : 83 - +
  • [30] A rail-to-rail, constant-gain CMOS OP-AMP
    Liang, YC
    Sheu, ML
    Hsu, WH
    [J]. PROCEEDINGS OF THE 2004 IEEE ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 1 AND 2: SOC DESIGN FOR UBIQUITOUS INFORMATION TECHNOLOGY, 2004, : 257 - 260