A BIST scheme for asynchronous logic

被引：2
|
作者：
Alves, VC [1 ]
Franca, FMG [1 ]
Granja, EP [1 ]
机构：
[1] Univ Fed Rio de Janeiro, COPPE Eletr, BR-21941 Rio De Janeiro, Brazil
来源：
SEVENTH ASIAN TEST SYMPOSIUM (ATS'98), PROCEEDINGS | 1998年
关键词：
D O I：
10.1109/ATS.1998.741575
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This work introduces a methodology to ease the implementation of BIST in asynchronous circuits. Scheduling by Edge Reversal (SER), a simple but powerful distributed synchronizer is used to implement a sequencer that allows resting the circuit at full speed The methodology, which allows the detection of topological faults, is proved correct. Low hardware overhead and the absence of deadlocks al-e the main characteristics of the proposed methodology.
引用
收藏
页码：27 / 32
页数：6
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