An Improved Low-offset and Low-power Design of Comparator for Flash ADC

This paper presents an offset-cancellation and low power cascaded comparator with new technique for flash Analog-to-Digital Converters. The improved structure cancels both input and output offset voltage by the feedback from outputs to common inputs. The total current consumption is reduced sharply for a clock circle with 1: 2 dutyratio. The improved comparator is implemented in 0.35 mu m CMOS process. The Spectre simulation results show that the offset voltage of the improved structure is 3.14996mV with sigma = 2.0347mV, and total current consumption is 17.59 mu A, while the offset voltage and total current consumption of the primary one is -5.649mV with sigma = 14.254mV and 57.18 mu A respectively.