An Improved Low-offset and Low-power Design of Comparator for Flash ADC

被引：0

作者：

Zhang Shuo ^{[1
]}

Wang Zongmin ^{[1
]}

Zhou Liang ^{[1
]}

机构：

[1] Beijing Microelect Tech Inst, Beijing, Peoples R China

来源：

ADVANCED MATERIALS, MECHANICS AND INDUSTRIAL ENGINEERING | 2014年 / 598卷

关键词：

Comparator; low-offset; low-power; flash ADC;

D O I：

10.4028/www.scientific.net/AMM.598.365

中图分类号：

TH [机械、仪表工业];

学科分类号：

0802 ;

摘要：

This paper presents an offset-cancellation and low power cascaded comparator with new technique for flash Analog-to-Digital Converters. The improved structure cancels both input and output offset voltage by the feedback from outputs to common inputs. The total current consumption is reduced sharply for a clock circle with 1: 2 dutyratio. The improved comparator is implemented in 0.35 mu m CMOS process. The Spectre simulation results show that the offset voltage of the improved structure is 3.14996mV with sigma = 2.0347mV, and total current consumption is 17.59 mu A, while the offset voltage and total current consumption of the primary one is -5.649mV with sigma = 14.254mV and 57.18 mu A respectively.

引用

页码：365 / 370

页数：6

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