Thermal Resistance Modeling for the Electrothermal Layout of High-Power RF Transistors

This paper demonstrates a practical approach to developing a geometrically scalable thermal resistance model to optimize layout for improved electrical performance of high-power RF transistors. The model is developed using finite element-based simulations, which show very good agreement with measured results. The proposed modeling methodology pre-computes simulations over all possible layout considerations and the individual elements of the thermal resistance matrices are automatically approximated by thin-plate splines. This approach produces a model for use within a circuit simulator with virtually no overhead. We are able to scale the model up to 60 mm with less than than 2% error in the maximum predicted temperature rise.