An Efficient Bit Reduction Binary Multiplication Algorithm using Vedic Methods

被引：9
|
作者：
Paramasivam, M. E. [1 ]
Sabeenian, R. S. [1 ]
机构：
[1] Sona Coll Technol, Adv Res Ctr, SONA SIPRO, Salem, Tamil Nadu, India
来源：
2010 IEEE 2ND INTERNATIONAL ADVANCE COMPUTING CONFERENCE | 2010年
关键词：
Multipliers; Vedic Mathematics; bit reduction; binary multiplication;
D O I：
10.1109/IADCC.2010.5423043
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
An efficient technique for multiplying two binary numbers using limited power and time is presented in this paper. The work mainly focuses on speed of the multiplication operation of multipliers, by reducing the number of bits to be multiplied. The framework of the proposed algorithm is taken from Mathematical algorithms given in Vedas and is further optimized by use of some general arithmetic operations such as expansion and bit-shifting. The proposed algorithm was modeled using Verilog, a hardware description language. It was found that under a given 3.3 V supply voltage, the designed 4 bit multiplier dissipates a power of 47.35 mW. The propagation time of the proposed architecture was found to 6.63ns
引用
收藏
页码：25 / 28
页数：4
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