FPGA implementation of a spiking neural network for pattern matching

被引：0

作者：

Caron, Louis-Charles ^{[1
]}

Mailhot, Frederic ^{[1
]}

Rouat, Jean ^{[1
]}

机构：

[1] Univ Sherbrooke, Dept Genie Elect & Genie Informat, Sherbrooke, PQ J1K 2R1, Canada

来源：

2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2011年

关键词：

RECOGNITION;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A field programmable gate array (FPGA) implementation of a hardware spiking neural network is presented. The system is able to realize different signal processing tasks using the synchronization of oscillatory leaky integrate and fire neurons. The use of a bit slice architecture and short, local interconnections make it adaptable to projects of various scales. The system is also designed to efficiently process groups of synchronized neurons. A fully connected network of 648 neurons and 419904 synapses is implemented on a stand-alone Xilinx XC5VSX50T FPGA, processing up to 6M spikes/s. We describe the resource usage for the whole system as well as for each functional block, and illustrate the functioning of the circuit on a simple image recognition task.

引用

页码：649 / 652

页数：4

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