Reversible logic to cryptographic hardware: A new paradigm

被引:0
|
作者
Thapliyal, Himanshu [1 ]
Zwolinski, Mark [2 ]
机构
[1] Int Inst Informat Technol, Ctr VLSI & Embedded Syst Technol, Hyderabad 500032, Andhra Pradesh, India
[2] Univ Southampton, Elect & Comp Sci, Elect Syst Design Grp, Southampton, Hants, England
关键词
D O I
暂无
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
Differential Power Analysis (DPA) presents a major challenge to mathematically-secure cryptographic protocols. Attackers can break the encryption by measuring the energy consumed in the working digital circuit. To prevent this type of attack, this paper proposes the use of reversible logic for designing the ALU of a cryptosystem. Ideally, reversible circuits dissipate zero energy. Thus, it would be of great significance to apply reversible logic to designing secure cryptosystems. As far as is known, this is the first attempt to apply reversible logic to developing secure cryptosystems. In a prototype of a reversible ALU for a crypto-processor, reversible designs of adders and Montgomery multipliers are presented. The reversible designs of a carry propagate adder, four-to-two and five-to-two carry save adders are presented using a reversible TSG gate. One of the important properties of the TSG gate is that it can work singly as a reversible full adder. In order to design the reversible Montgomery multiplier, novel reversible sequential circuits are also proposed which are integrated with the proposed adders to design a reversible modulo multiplier. It is intended that this paper will provide a starting point for developing cryptosystems secure against DPA attacks.
引用
收藏
页码:342 / +
页数:2
相关论文
共 50 条
  • [21] DPA on faulty cryptographic hardware and countermeasures
    Kulikowski, Konrad J.
    Karpovsky, Mark G.
    Taubin, Alexander
    [J]. FAULT DIAGNOSIS AND TOLERANCE IN CRYPTOGRAPHY, PROCEEDINGS, 2006, 4236 : 211 - 222
  • [22] Hardware Implementation of Ultralightweight Cryptographic Protocols
    Ul Ain, Qurat
    Mujahid, Umar
    Najam-ul-islam, M.
    [J]. 2015 INTERNATIONAL CONFERENCE ON COMPUTING, COMMUNICATION AND SECURITY (ICCCS), 2015,
  • [23] Cryptographic Hardware & Embedded Systems for Communications
    Sklavos, Nicolas
    [J]. 2012 IEEE FIRST AESS EUROPEAN CONFERENCE ON SATELLITE TELECOMMUNICATIONS (ESTEL), 2012,
  • [24] Supplemental cryptographic hardware for smart cards
    Trichina, E
    Bucci, M
    De Seta, D
    Luzzi, R
    [J]. IEEE MICRO, 2001, 21 (06) : 26 - 35
  • [25] A new reversible logic gate and its applications
    Vasudevan, DP
    Lala, PK
    [J]. ESA'04 & VLSI'04, PROCEEDINGS, 2004, : 480 - 484
  • [26] Tamper-resistant cryptographic hardware
    Fujino, Takeshi
    Kubota, Takaya
    Shiozaki, Mitsuru
    [J]. IEICE ELECTRONICS EXPRESS, 2017, 14 (02): : 1 - 13
  • [27] A new heuristic algorithm for reversible logic synthesis
    Kerntopf, P
    [J]. 41ST DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2004, 2004, : 834 - 837
  • [28] On the Synthesis of Attack Tolerant Cryptographic Hardware
    Mathew, J.
    Banerjee, S.
    Rahaman, H.
    Pradhan, D. K.
    Mohanty, S. P.
    Jabir, A. M.
    [J]. PROCEEDINGS OF THE 2010 18TH IEEE/IFIP INTERNATIONAL CONFERENCE ON VLSI AND SYSTEM-ON-CHIP, 2010, : 286 - 291
  • [29] Hardware Trojans in Wireless Cryptographic ICs
    Jin, Yier
    Makris, Yiorgos
    [J]. IEEE DESIGN & TEST OF COMPUTERS, 2010, 27 (01): : 26 - 35
  • [30] A New Security Proof of Practical Cryptographic Devices Based on Hardware, Software and Protocols
    Wang, An
    Li, Zheng
    Yang, Xianwen
    Yu, Yanyan
    [J]. INFORMATION SECURITY PRACTICE AND EXPERIENCE, 2011, 6672 : 386 - 400