A novel vertical bottom-gate polysilicon thin film transistor with self-aligned offset

被引：0

作者：

Lai, CS ^{[1
]}

Lee, CL ^{[1
]}

Lei, TF ^{[1
]}

Chern, HN ^{[1
]}

机构：

[1] NATL CHIAO TUNG UNIV,INST ELECTR,HSINCHU 30039,TAIWAN

来源：

IEEE ELECTRON DEVICE LETTERS | 1996年 / 17卷 / 05期

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A novel device structure for the vertical bottom polysilicon gate thin film transistor (TFT) with a self-align offset drain is proposed and demonstrated, The new VTFT allows a deep-submicron channel length, which is determined by the thickness of the active polysilicon film, not by the lithographic system resolution, The self-alignment offset drain reduces the leakage current, as a result, it exhibits good device performance.

引用

页码：199 / 201

页数：3

共 50 条

[1] Implementation of fully self-aligned bottom-gate MOS transistor
Zhang, SD
Han, RQ
Zhang, ZK
Huang, R
Ko, PK
Chan, MS
IEEE ELECTRON DEVICE LETTERS, 2002, 23 (10) : 618 - 620
[2] A new self-aligned offset staggered polysilicon thin-film transistor
Han, JI
Yang, GY
Han, CH
IEEE ELECTRON DEVICE LETTERS, 1999, 20 (08) : 381 - 383
[3] A Bottom-Gate Metal-Oxide Thin-Film Transistor With Self-Aligned Source/Drain Regions
Xia, Zhihe
Lu, Lei
Li, Jiapeng
Kwok, Hoi-Sing
Wong, Man
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2018, 65 (07) : 2820 - 2826
[4] A self-aligned offset polysilicon thin-film transistor using photoresist reflow
Han, JI
Han, CH
IEEE ELECTRON DEVICE LETTERS, 1999, 20 (09) : 476 - 477
[5] Novel Fabrication Method for Self-Aligned Bottom-Gate Oxide TFTs
Nakata, Mitsuru
Tsuji, Hiroshi
Fujisaki, Yoshihide
Sato, Hiroto
Nakajima, Yoshiki
Takei, Tatsuya
Yamamoto, Toshihiro
IDW/AD '12: PROCEEDINGS OF THE INTERNATIONAL DISPLAY WORKSHOPS, PT 1, 2012, 19 : 431 - 432
[6] A Novel Self-Aligned Double-Channel Polysilicon Thin-Film Transistor
Chien, Feng-Tso
Chen, Chii-Wen
Lee, Tien-Chun
Wang, Chi-Ling
Cheng, Ching-Hwa
Kang, Tsung-Kuei
Chiu, Hsien-Chin
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2013, 60 (02) : 799 - 804
[7] Self-Aligned Bottom-Gate InGaZnO Thin-Film Transistor with Source and Drain Regions Formed by Selective Deposition of Fluorinated SiNx Passivation
Furuta, Mamoru
Jiang, Jingxin
Tatsuoka, Gengo
Wang, Dapeng
THIN FILM TRANSISTORS 12 (TFT 12), 2014, 64 (10): : 53 - 58
[8] SELF-ALIGNED BOTTOM-GATE SUBMICROMETER-CHANNEL-LENGTH A-SI-H THIN-FILM TRANSISTORS
BUSTA, HH
POGEMILLER, JE
STANDLEY, RW
MACKENZIE, KD
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1989, 36 (12) : 2883 - 2888
[9] Narrow width effects of bottom-gate polysilicon thin film transistors
Yaung, DN
Fang, YK
Hwang, KC
Lee, KY
Wu, KH
Ho, JJ
Chen, CY
Wang, YJ
Liang, MS
Lee, JY
Wuu, SG
IEEE ELECTRON DEVICE LETTERS, 1998, 19 (11) : 429 - 431
[10] A viable self-aligned bottom-gate MOS transistor technology for deep submicron 3-D SRAM
Zhang, SD
Chan, ACK
Han, RQ
Huang, R
Liu, XY
Wang, YY
Ko, PK
Chan, MS
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2003, 50 (09) : 1952 - 1960

← 1 2 3 4 5 →