A DSP HEVC decoder implementation based on OpenHEVC

被引：0
|
作者：
Pescador, F. [1 ]
Cano, J. P. [1 ]
Garrido, M. J. [1 ]
Juarez, E. [1 ]
Raulet, M. [2 ]
机构：
[1] Univ Politecn Madrid, Software Technol & Multimedia Syst Res Ctr CITSEM, E-28040 Madrid, Spain
[2] IETR, INSA, Rennes, France
来源：
2014 IEEE INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS (ICCE) | 2014年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The new High Efficiency Video Codec (HEVC) standard will replace H.264 soon in consumer multimedia applications. The open source project OpenHEVC is working on an efficient implementation of the HEVC decoder in C language. In this paper, an HEVC decoder based on OpenHEVC for DSP technology is presented. The tests show that it outperforms by 2.3 a previously developed HM9.0-based decoder for the same DSP.
引用
收藏
页码：63 / 64
页数：2
相关论文
共 50 条
  • [41] Real time implementation and optmization of MP3 decoder on DSP
    Samuel, Benix
    Jhunjhunwala, Ashok
    2008 CANADIAN CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING, VOLS 1-4, 2008, : 665 - 668
  • [42] FPGA Implementation of a Full HD Real-time HEVC Main Profile Decoder
    Engelhardt, Denis
    Moeller, Jan
    Hahlbeck, Jan
    Stabernack, Benno
    IEEE TRANSACTIONS ON CONSUMER ELECTRONICS, 2014, 60 (03) : 476 - 484
  • [43] High-throughput HW-SW implementation for MV-HEVC decoder
    Liu, Wei
    Li, Wei
    Un, Park Sang
    Cho, Yong Beom
    2018 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC), 2018, : 226 - 228
  • [44] Implementation of Multi-bin CABAC Decoder in HEVC/H.265 on FPGA
    Wahiba, Menasri
    Abdellah, Skoudarli
    Aichouche, Belhadj
    ADVANCES IN COMPUTING SYSTEMS AND APPLICATIONS, 2019, 50 : 113 - 123
  • [45] Implementation and Optimization of I-frame in AVS1-P2 Decoder Based on DSP
    Wang, Ban
    Zhou, Jianyang
    Chen, Meifen
    2008 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS PROCEEDINGS, VOLS 1 AND 2, 2008, : 846 - 849
  • [46] An Improved Hypothetical Reference Decoder For HEVC
    Deshpande, Sachin
    Hannuksela, Miska M.
    Kazui, Kimihiko
    Schierl, Thomas
    VISUAL INFORMATION PROCESSING AND COMMUNICATION IV, 2013, 8666
  • [47] Pipelining the HEVC Decoder on ZedBoard Plateform
    SME, Habib, I
    SMIRI, Kamel
    JEMA, Abderrazak, I
    PROCEEDINGS OF 2016 11TH INTERNATIONAL DESIGN & TEST SYMPOSIUM (IDT), 2016, : 7 - 12
  • [48] HEVC Decoder Analysis on ARM Processor
    Ayadi, Lella Aicha
    Damak, Taheni
    Loukil, Hassen
    Ben Ayed, Mohamed Ali
    Masmoudi, Nouri
    2018 15TH INTERNATIONAL MULTI-CONFERENCE ON SYSTEMS, SIGNALS AND DEVICES (SSD), 2018, : 842 - 845
  • [49] Neural network and DSP based decoder for DTMF signals
    Daponte, P
    Grimaldi, D
    Micheali, L
    IEE PROCEEDINGS-SCIENCE MEASUREMENT AND TECHNOLOGY, 2000, 147 (01) : 34 - 40
  • [50] Design of parallel HEVC decoder based on Multi-core platform
    Fang, Di
    Hu, Dong
    WIRELESS COMMUNICATION AND SENSOR NETWORK, 2016, : 1003 - 1009
12345