Multiple 1:N interpolation fir filter design based on a single architecture

A VLSI architecture for multiple 1:N interpolation FIR filter is proposed for QPSK modulation in WLL. Multiple filters are operated synchronously and N outputs are generated in case of 1:N interpolation. But the architecture and the operating frequency are the same as those of single FIR filter architecture except having pipeline registers. Because of using a single architecture, proposed architecture can be implemented with less chip area. The power consumption is not increased because its operating frequency is the same as that of single architecture. When N is 4, four-output 1:4 interpolation filter is designed using VHDL logic synthesis. The number of gates and operating frequency are compared with those of transversal FIR filter design method and look-up table design method.