FIR Filter Design Based On FPGA

被引：1
|
作者：
Zheng Jiayu [1 ]
Wei Zhenhua [1 ]
机构：
[1] East China Univ Technol, Sch Informat Engn, Nanchang 330013, Jiangxi, Peoples R China
来源：
2018 10TH INTERNATIONAL CONFERENCE ON MEASURING TECHNOLOGY AND MECHATRONICS AUTOMATION (ICMTMA) | 2018年
关键词：
FIR; FPGA; MODELSIM simulation; Verilog HDL;
D O I：
10.1109/ICMTMA.2018.00016
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
FIR (Finite Impulse Response) filters: the finite impulse response filter is the most basic components in digital signal processing systems and are widely used in communications, image processing, and pattern recognition. Based on FPGA (editable logic device) to achieve FIR filter, not only take into account the fixed-function DSP-specific chip real-time, but also has the DSP processor flexibility. The combination of FPGA and DSP technology can further improve integration, increase work speed and expand system capabilities.
引用
收藏
页码：36 / 40
页数：5
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