High Speed Low Power 64-Bit Comparator Designed Using Current Comparison Based Domino Logic

The rapid growth in CMOS technology with the shrinking device size towards 22 nm has allowed for placement of billions of transistors on a single microprocessor chip. To achieve very high system performance, domino logic styles are widely employed in high performance VLSI chips together with aggressive technology scaling. Comparators are widely used in central processing units (CPUs) and microcontrollers (MCUs). In this paper, a 64 bit comparator circuit is proposed which has a lower leakage and higher noise immunity without dramatic speed degradation compared to high speed domino logic, leakage current replica keeper domino logic and diode footed domino logic. This circuit is based on comparison of mirrored current of the pull up network (PUN) with its worst case leakage current. Current comparison based domino technique reduces the parasitic capacitance on the dynamic node using a small keeper transistor, which reduces the contention current, power consumption and also the delay of the circuit. Simulation results of 64 bit comparator designed using a 22nm high performance predictive technology model demonstrate 51% power reduction compared to a standard domino circuits for 64 bit comparator.