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- [3] A Novel Planar Floating-Gate (FG)/Charge-Trapping (CT) NAND Device Using BE-SONOS Inter-Poly Dielectric (IPD) 2009 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, 2009, : 773 - +
- [5] Hierarchical Constrained Coding for Floating-Gate to Floating-Gate Coupling Mitigation in Flash Memory 2011 IEEE GLOBAL TELECOMMUNICATIONS CONFERENCE (GLOBECOM 2011), 2011,
- [7] Nitrided GdTiO as Charge-Trapping Layer for Flash Memory Applications 2012 IEEE 11TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT-2012), 2012, : 927 - 929
- [8] TID Radiation Impacts on Charge-trapping Macaroni 3D NAND Flash Memory 2020 IEEE INTERNATIONAL SYMPOSIUM ON THE PHYSICAL AND FAILURE ANALYSIS OF INTEGRATED CIRCUITS (IPFA), 2020,