Sub-Sampling PLL For Millimeter Wave Applications: An Overview

被引：0

作者：

Gao, Xiang ^{[1
]}

机构：

[1] Zhejiang Univ, Hangzhou, Peoples R China

来源：

2019 IEEE MTT-S INTERNATIONAL MICROWAVE CONFERENCE ON HARDWARE AND SYSTEMS FOR 5G AND BEYOND (IMC-5G) | 2019年

关键词：

Clock generation; clock multiplier; frequency multiplication; frequency synthesizer; phase locked loop; low jitter; low phase noise; low power; sub-sampling phase detector; sub-sampling PLL; PLL FOM; PHASE NOISE; LOOP;

D O I：

10.1109/imc-5g47857.2019.9160380

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

The sub-sampling PLL utilizes a PD that sub-samples the high frequency VCO output with the reference clock. The PD and CP noise in this PLL is greatly attenuated by the high phase detection gain due to the high VCO dv/dt slew rate. It is now a proven PLL architecture and widely used for achieving low phase noise or integrated jitter yet with low power consumption. This article reviews the development of the sub-sampling PLL techniques and their usage in the millimeter wave applications.

引用

页数：5

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