A PLL with Ultra Low Phase Noise for Millimeter Wave Applications

被引：0

作者：

Gai, Xiaolei ^{[1
]}

Liu, Gang ^{[1
]}

Chartier, Sebastien ^{[2
,3
]}

Trasser, Andreas ^{[1
]}

Schumacher, Hermann ^{[1
]}

机构：

[1] Univ Ulm, Inst Elect Device & Circuits, Albert Einstein Allee 45, D-89081 Ulm, Germany

[2] EADS Def & Secur T R Modules, D-89077 Ulm, Germany

[3] MMICs, D-89077 Ulm, Germany

来源：

40TH EUROPEAN MICROWAVE CONFERENCE | 2010年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An ultra low noise phase locked loop (PLL) for millimeter wave applications is presented. The complete design includes a mixer type phase detector, a divide-by-32 frequency divider, a VCO and an off-chip active low pass filter. A method for the phase noise optimization of the PLL is described. The chip was designed using a 0.8 mu m SiGe HBT technology. The frequency can be tuned from 29.9 GHz to 33.1 GHz. The output phase noise is around -112 dBc/Hz at 1 MHz offset.

引用

页码：69 / 72

页数：4

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