Reliability and characteristics of wafer-level chip-scale packages under current stress

被引:2
|
作者
Chen, Po-Ying [1 ]
Kung, Heng-Yu [2 ,3 ]
Lai, Yi-Shao [3 ]
Tsai, Ming Hsiung [2 ]
Yeh, Wen-Kuan [2 ]
机构
[1] I Shou Univ, Dept Informat Engn, Dashu Township 840, Kaohsiung Cty, Taiwan
[2] Natl Kaohsiung Univ, Dept Elect Engn, Kaohsiung 811, Taiwan
[3] Adv Semicond Engn Inc, Stress Reliabil Lab, Kaohsiung 811, Taiwan
关键词
wafer level chip scale package; mean time to failure (MTTF); current stressing; smart mount technology (SMT); reliability; electromigration; thermomigration;
D O I
10.1143/JJAP.47.819
中图分类号
O59 [应用物理学];
学科分类号
摘要
In this work, we present a novel approach and method for elucidating the characteristics of wafer-level chip-scale packages (WLCSPs) for electromigration (EM) tests. The die in WLCSP was directly attached to the substrate via a soldered interconnect. The shrinking of the area of the die that is available for power, and the solder bump also shrinks the volume and increases the density of electrons for interconnect efficiency. The bump current density now approaches to 10(6)A/cm(2), at which point the EM becomes a significant reliability issue. As known, the EM failure depends on numerous factors, including the working temperature and the under bump metallization (UBM) thickness. A new interconnection geometry is adopted extensively with moderate success in overcoming larger mismatches between the displacements of components during current and temperature changes. Both environments and testing parameters for WLCSP are increasingly demanded. Although failure mechanisms are considered to have been eliminated or at least made manageable, new package technologies are again challenging its process, integrity and reliability. WLCSP technology was developed to eliminate the need for encapsulation to ensure compatibility with smart-mount technology (SMT). The package has good handing properties but is now facing serious reliability problems. In this work, we investigated the reliability of a WLCSP subjected to different accelerated current stressing conditions at a fixed ambient temperature of 125 degrees C. A very strong correlation exists between the mean time to failure (MTTF) of the WLCSP test vehicle and the mean current density that is carried by a solder joint. A series of current densities were applied to the WLCSP architecture; Black's power law was employed in a failure mode simulation. Additionally, scanning electron microscopy (SEM) was adopted to determine the differences existing between high- and low-current-density failure modes.
引用
收藏
页码:819 / 823
页数:5
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