An experimental investigation of current stressing on wafer-level chip-scale packages

被引：0
|
作者：
Lai, Yi-Shao [1 ]
Kung, Heng-Yu [1 ,2 ]
Chen, Po-Ying [3 ]
Yeh, Wen-Kuan [2 ]
机构：
[1] Adv Semicond Engn Inc, Stress Reliabil Lab, 26 Chin 3rd Rd,Nantze Export Proc Zone 811, Kaohsiung, Taiwan
[2] Natl Univ Kaohsiung, Dept Elect Engn, Kaohsiung, Taiwan
[3] Ming Chuan Univ, Dept Informat & Telecommun, Taoyuan, Taiwan
来源：
EPTC 2006: 8TH ELECTRONIC PACKAGING TECHNOLOGY CONFERENCE, VOLS 1 AND 2 | 2006年
关键词：
D O I：
暂无
中图分类号：
T [工业技术];
学科分类号：
08 ;
摘要：
We investigated the reliability of a board-level wafer-level chip-scale package (WLCSP) subjected to different accelerated current stressing conditions at a fixed ambient temperature of 125 T. A reasonably good correlation between mean-time-to-failure of the WLCSP test vehicle and the average current density carried by a solder joint was obtained. Moreover, the trace breakage was identified as the mandatory failure mode under these current stressing conditions. In-situ observations were also conducted to further identify this particular failure mode.
引用
收藏
页码：582 / 584
页数：3
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