Management of power and performance with stress memorization technique for 45nm CMOS

被引：13

作者：

Eiho, A. ^{[1
]}

Sanuki, T. ^{[1
]}

Morifuji, E. ^{[1
]}

Iwamoto, T. ^{[2
]}

Sudo, G. ^{[1
]}

Fukasaku, K. ^{[3
]}

Ota, K. ^{[3
]}

Sawada, T. ^{[1
]}

Fuji, O. ^{[1
]}

Nii, H. ^{[1
]}

Togo, M. ^{[2
]}

Ohno, K. ^{[3
]}

Yoshida, K. ^{[1
]}

Tsuda, H. ^{[2
]}

Ito, T. ^{[1
]}

Shiozaki, Y. ^{[1
]}

Fuji, N. ^{[1
]}

Yamazaki, H. ^{[1
]}

Nakazawa, M. ^{[3
]}

Iwasa, S. ^{[1
]}

Muramatsu, S. ^{[2
]}

Nagaoka, K. ^{[3
]}

Iwai, M. ^{[1
]}

Ikeda, M. ^{[2
]}

Saito, M. ^{[3
]}

Naruse, H. ^{[1
]}

Enomoto, Y. ^{[3
]}

Kitano ^{[2
]}

Yamada, S. ^{[1
]}

Imai, K. ^{[2
]}

Nagashima, N. ^{[3
]}

Kuwata, T. ^{[2
]}

Matsuoka, F. ^{[1
]}

机构：

[1] Toshiba Co Ltd, Adv CMOS Technol Grp, Adv Log Technol Dept, Syst LSI Div,Isogo Ku, 8 Shinsugita Cho, Yokohama, Kanagawa 2102582, Japan

[2] NEC Elect Corp, Isogo Ku, Yokohama, Kanagawa 2102582, Japan

[3] Sony Corp, Isogo Ku, Yokohama, Kanagawa 2102582, Japan

来源：

2007 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2007年

关键词：

D O I：

10.1109/VLSIT.2007.4339699

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The effect of stress memorization technique (SMT) in performance and power reduction is maximized by choosing the appropriate stressor with large stress change by spike RTA. 30% mobility enhancement and 60% reduction of gate leakage have been achieved simultaneously. Stress distribution in channel region for SMT is confirmed to be uniform, hence layout dependency is minimized and performance is maximized in aggressively scaled CMOS with dense gate pitch rule(190nm) in 45nm technology node.

引用

页码：218 / +

页数：2

共 50 条

[1] Leakage Power Reduction for Domino Circuits in 45nm CMOS Technologies
Pandey, A. K.
Kaur, S.
Mishra, R. A.
Nagaria, R. K.
2012 2ND INTERNATIONAL CONFERENCE ON POWER, CONTROL AND EMBEDDED SYSTEMS (ICPCES 2012), 2012,
[2] RF Modeling of 45nm Low-Power CMOS Technology
Wang, Jing
Li, Hongmei
Pan, Li-Hong
Gogineni, Usha
Groves, Robert
Jagannathan, Basanth
Na, Myung-Hee
Tonti, William
Wachnik, Richard
NANOTECH CONFERENCE & EXPO 2009, VOL 3, TECHNICAL PROCEEDINGS: NANOTECHNOLOGY 2009: BIOFUELS, RENEWABLE ENERGY, COATINGS FLUIDICS AND COMPACT MODELING, 2009, : 628 - +
[3] Bandpass Power Divider Design in Advanced 45nm CMOS Process
Kou, Zhonghao
Pei, Xiaoqing
Zhou, Hang
Wang, Xudong
2024 INTERNATIONAL CONFERENCE ON MICROWAVE AND MILLIMETER WAVE TECHNOLOGY, ICMMT, 2024,
[4] A 0.65V Embedded SDRAM with Smart Boosting and Power Management in a 45nm CMOS Technology
Pyo, Suk-Soo
Kim, Jun-Sung
Kim, Jung-Han
Jung, Hyun-Taek
Song, Tae-Joong
Lee, Cheol-Ha
Kim, Gyu-Hong
Lee, Young-Keun
Kim, Kee-Sup
2012 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2012,
[5] A High Frequency CMRR improvement technique for Differential Amplifiers in 45nm CMOS
Nagulapalli, R.
Hayatleh, K.
Barker, S.
Reddy, B. Naresh Kumar
Seetharamulu, B.
2019 10TH INTERNATIONAL CONFERENCE ON COMPUTING, COMMUNICATION AND NETWORKING TECHNOLOGIES (ICCCNT), 2019,
[6] 45nm/32nm CMOS - Challenge and perspective
Ishimaru, Kazunari
ESSCIRC 2007: PROCEEDINGS OF THE 33RD EUROPEAN SOLID-STATE CIRCUITS CONFERENCE, 2007, : 32 - 35
[7] 45nm/32nm CMOS - Challenge and perspective -
Ishimaru, Kazunari
ESSDERC 2007: PROCEEDINGS OF THE 37TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2007, : 32 - +
[8] CMOS Level Shifters for Low Power Applications using 45nm Technology
Swaroop, S.
Ravindra, K. S.
2018 3RD INTERNATIONAL CONFERENCE ON ELECTRICAL, ELECTRONICS, COMMUNICATION, COMPUTER, AND OPTIMIZATION TECHNIQUES (ICEECCOT - 2018), 2018, : 867 - 872
[9] Millimeter-Wave Power Amplifiers in 45nm CMOS SOI Technology
Chen, Jing-Hwa
Helmi, Sultan R.
Mohammadi, Saeed
2011 IEEE INTERNATIONAL SOI CONFERENCE, 2011,
[10] High Performance Digital to Analog Converter Using CMOS 45nm Technology
Raju, David Solomon Y.
Shyamala, K.
Sumalatha, Ch
Sunilkumar, J.
PROCEEDINGS OF THE 6TH INTERNATIONAL CONFERENCE ON INVENTIVE COMPUTATION TECHNOLOGIES (ICICT 2021), 2021, : 357 - 361

← 1 2 3 4 5 →