Challenges in system-level design

被引:0
|
作者
Wolf, W [1 ]
机构
[1] Princeton Univ, Dept Elect Engn, Princeton, NJ 08544 USA
关键词
D O I
暂无
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
This paper summarizes some of the challenges presented by very large integrated circuits. Today's embedded applications require not just complex algorithms but multi-tasking systems that perform several different types of operations on the data. Those applications are run on systems-on-chips that embody complex, heterogeneous architectures. Furthermore, systems-on-chips are connected into even larger systems. The large amounts of state in systems-on-chips, along with the interactions between traditional functionality and performance, mean that we must expand the scope of system design and verification activities. We still need to solve all the traditional design problems, but we must also develop new methodologies that allow us to design and verify the long-term behavior of the system.
引用
收藏
页码:1 / 5
页数:5
相关论文
共 50 条
  • [31] Heterogeneous System-Level Package Integration - Trends and Challenges
    Lee, Frank J. C.
    Wong, Mei
    Tzou, Jerry
    Yuan, Jonathan
    Chang, Daniel
    Rusu, Stefan
    2020 IEEE SYMPOSIUM ON VLSI TECHNOLOGY, 2020,
  • [32] Research of design for system-level testability and system partition
    Li, TG
    Huang, KL
    Lian, GY
    Wang, BL
    ICEMI 2005: Conference Proceedings of the Seventh International Conference on Electronic Measurement & Instruments, Vol 1, 2005, : 242 - 245
  • [33] Current Challenges in Component-level and System-level ESD Simulation
    Rosenbaum, Elyse
    Meng, Kuo-Hsuan
    Xiu, Yang
    Thomson, Nicholas
    2015 ASIA-PACIFIC INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (APEMC), 2015, : 333 - 336
  • [34] System-level design for partially reconfigurable hardware
    Qu, Yang
    Tiensyrja, Kari
    Soininen, Juha-Pekka
    Nurmi, Jari
    2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, 2007, : 2738 - +
  • [35] System-level design for nano-electronics
    Atienza, David
    Bobba, Shashi Kanth
    Poli, Massimo
    De Micheli, Giovanni
    Benini, Luca
    2007 14TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-4, 2007, : 747 - +
  • [36] RISC VLSI DESIGN FOR SYSTEM-LEVEL PERFORMANCE
    ROWEN, C
    CRUDELE, L
    FREITAS, D
    HANSEN, C
    HUDSON, E
    KINSEL, J
    MOUSSOURIS, J
    PRZYBYLSKI, S
    RIORDAN, T
    VLSI SYSTEMS DESIGN, 1986, 7 (03): : 81 - &
  • [37] ARCHITECTURAL MODELS ARE KEY TO SYSTEM-LEVEL DESIGN
    JAIN, PP
    ELECTRONIC DESIGN, 1991, 39 (06) : 57 - &
  • [38] Design languages vie for system-level dominance
    Maliniak, D
    ELECTRONIC DESIGN, 2001, 49 (20) : 53 - +
  • [39] System-Level Design Optimization of a Hybrid Tug
    Hofman, T.
    Naaborg, M.
    Sciberras, E.
    2017 IEEE VEHICLE POWER AND PROPULSION CONFERENCE (VPPC), 2017,
  • [40] Design optimization with system-level reliability constraints
    McDonald, M.
    Mahadevan, S.
    JOURNAL OF MECHANICAL DESIGN, 2008, 130 (02)