A Stacked 6.5-GHz 29.6-dBm Power Amplifier in Standard 65-nm CMOS

被引：0
|
作者：
Fathi, Maryam [1 ]
Su, David K. [1 ]
Wooley, Bruce A. [1 ]
机构：
[1] Stanford Univ, Stanford, CA 94305 USA
来源：
IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE 2010 | 2010年
关键词：
EFFICIENCY;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A stacked amplifier architecture has been used to achieve high RF output power levels in sub-100nm CMOS. The stacking makes it possible to both operate the power amplifier (PA) from a large supply voltage and implement RF power combining. As a proof of concept, a 6.5-GHz PA has been integrated in a 65-nm standard CMOS technology. The amplifier achieves 27.4-dBm output power with an efficiency of 19.2% at 6.5 GHz when driven from a 3.6-V supply voltage and 29.6-dBm output power with an efficiency of 20.3%, when driven from a 4.6-V supply voltage.
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页数：4
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