A 0.5-6 GHz 25.6 dBm Fully Integrated Digital Power Amplifier in 65-nm CMOS

被引：0

作者：

Wang, Hongrui ^{[1
]}

Hashemi, Hossein ^{[1
]}

机构：

[1] Univ So Calif, Dept Elect Engn, Los Angeles, CA 90089 USA

来源：

2014 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS SYMPOSIUM | 2014年

关键词：

Digital power amplifier; transformer combiner; load modulation; software defined radio; CMOS;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a 0.5-6 GHz fully-integrated Digital Power Amplifier (DPA) in 65 nm CMOS technology. Transformer-based class-E/F power amplifiers with zero-voltage switching are designed to achieve high power and high efficiency across a wide frequency band. A Single-Pole Triple-Throw (SP3T) switch featuring low insertion loss and high isolation is implemented to select the output of one of the three sub-band DPAs covering approximately 0.5-1.3 GHz, 1.3-3.2 GHz, and 3.2-6 GHz, respectively. Measurement results show a peak output power of 25.6-22.8 dBm with a peak drain efficiency of 34%-20% across 0.5-6 GHz.

引用

页码：409 / 412

页数：4

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