Generic VLSI architecture for block-matching motion estimation algorithms

被引：0
|
作者：
He, ZL [1 ]
Liou, ML [1 ]
Chan, PCH [1 ]
Tsui, CY [1 ]
机构：
[1] Hong Kong Univ Sci & Technol, Dept Elect & Elect Engn, Kowloon, Hong Kong
来源：
INTERNATIONAL JOURNAL OF IMAGING SYSTEMS AND TECHNOLOGY | 1998年 / 9卷 / 04期
关键词：
D O I：
10.1002/(SICI)1098-1098(1998)9:4<257::AID-IMA8>3.0.CO;2-9
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this article, a generic VLSI architecture which is both programmable and scalable is proposed for block-matching motion estimation algorithms. Various motion estimation algorithms can be implemented using the proposed architecture by organizing the individual search positions (checking points) into checking vectors. A checking vector is processed in parallel by fully exploiting its data dependency. The optimal choice for the size of checking vector is discussed based on the design tradeoffs among processing speed, silicon area, and I/O bandwidth. Appropriate designs are recommended for various video applications. (C) 1998 John Wiley & Sons, Inc. Int J Imaging Syst Technol, 9, 267-273, 1998.
引用
收藏
页码：257 / 273
页数：17
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