FPGA-Based Dynamically Reconfigurable SQL Query Processing

被引:27
|
作者
Ziener, Daniel [1 ,4 ]
Bauer, Florian [1 ]
Becher, Andreas [1 ]
Dennl, Christopher [1 ]
Meyer-Wegener, Klaus [2 ]
Schuerfeld, Ute [3 ]
Teich, Juergen [1 ]
Vogt, Joerg-Stephan [3 ]
Weber, Helmut [3 ]
机构
[1] Univ Erlangen Nurnberg, Cauerstr 11, D-91058 Erlangen, Germany
[2] Univ Erlangen Nurnberg, Martensstr 3, D-91058 Erlangen, Germany
[3] IBM Deutschland Res & Dev GmbH, Schonaicher Str 220, D-71032 Boblingen, Germany
[4] Hamburg Univ Technol TUHH, Schwarzenberg Campus 3 E, D-21073 Hamburg, Germany
关键词
Design; Performance; FPGA; dynamic partial reconfiguration; SQL processing; reconfigurable computing;
D O I
10.1145/2845087
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In this article, we propose an FPGA-based SQL query processing approach exploiting the capabilities of partial dynamic reconfiguration of modern FPGAs. After the analysis of an incoming query, a query-specific hardware processing unit is generated on the fly and loaded on the FPGA for immediate query execution. For each query, a specialized hardware accelerator pipeline is composed and configured on the FPGA from a set of presynthesized hardware modules. These partially reconfigurable hardware modules are gathered in a library covering all major SQL operations like restrictions and aggregations, as well as more complex operations such as joins and sorts. Moreover, this holistic query processing approach in hardware supports different data processing strategies including row-as column-wise data processing in order to optimize data communication and processing. This article gives an overview of the proposed query processing methodology and the corresponding library of modules. Additionally, a performance analysis is introduced that is able to estimate the processing time of a query for different processing strategies and different communication and processing architecture configurations. With the help of this performance analysis, architectural bottlenecks may be exposed and future optimized architectures, besides the two prototypes presented here, may be determined. Categories and Subject Descriptors: B.5.1 [Register-Transfer-Level Implementation]: Design-Data-path design; C.3 [Special-Purpose and Application-based Systems]: Microprocessor/Microcomputer Applications; H.2.4 [Database Management]: Systems-Query processing
引用
收藏
页数:24
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