共 50 条
- [1] Pushing Multiple Patterning in Sub-10nm: Are We Ready? [J]. 2015 52ND ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2015,
- [2] Extension of patterning technologies down to sub-10nm half pitch [J]. ADVANCED ETCH TECHNOLOGY FOR NANOPATTERNING II, 2013, 8685
- [4] New Lithography Technology for Sub-10nm Patterning with Shrinking Organic Material [J]. ALTERNATIVE LITHOGRAPHIC TECHNOLOGIES VI, 2014, 9049
- [5] Resiliency Challenges in sub-10nm Technologies [J]. 2015 IEEE 33RD VLSI TEST SYMPOSIUM (VTS), 2015,
- [6] A high chi track-compatible DSA for sub-10nm L/S patterning [J]. ADVANCES IN PATTERNING MATERIALS AND PROCESSES XXXIV, 2017, 10146
- [7] PMMA removal selectivity to PS using dry etch approach: Sub-10nm patterning application [J]. ADVANCED ETCH TECHNOLOGY FOR NANOPATTERNING V, 2016, 9782
- [8] Source/Drain Architecture Design of Vertical Channel Nanowire FET for sub-10nm node [J]. 2016 13TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT), 2016, : 1008 - 1010