A Reconfigurable Hardware Platform Implementation for Software Defined Radio using Dynamic Partial Reconfiguration on Xilinx Zynq FPGA

Dynamic Partial Reconfiguration (DPR) can be used efficiently to implement a reconfigurable hardware platform for Software Defined Radio system that supports multiple wireless standards. This method optimizes several design metrics such as hardware resources, power, and reconfiguration time. Nevertheless, partitioning is a challengeable issue in the DPR flow. In this work, we implement two design approaches: one with single-partition approach and another with multi-partitions using a partitioning algorithm, introduced in the literature. A complete DPR design flow is discussed. Also, a comparison between the two approaches is evaluated on a Xilinx Zynq FPGA. It is observed that the multi-partitions-based approach gives 16% less reconfiguration time while reducing the reconfiguration area and power consumption by 4.5% and 9.8% respectively.