Optimized RISC architecture for multiple-precision modular arithmetic

被引:0
|
作者
Grossschädl, J [1 ]
Kamendje, GA [1 ]
机构
[1] Graz Univ Technol, Inst Appl Informat Proc & Commun, A-8010 Graz, Austria
来源
关键词
RSA algorithm; Montgomery multiplication; finely integrated operand scanning (FIOS); multi-application smart cards;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Public-key cryptosystems normally spend most of their execution time in a small fraction of the program code, typically in an inner loop. The performance of these critical code sections can be significantly improved by customizing the processor's instruction set and microarchitecture, respectively. This paper shows the advantages of instruction set extensions to accelerate the processing of cryptographic workloads such as long integer modular arithmetic. We define two custom instructions for performing multiply-and-add operations on unsigned integers (single-precision words). Both instructions can be efficiently executed by a (32 x 32 + 32 + 32)-bit multiply/accumulate (MAC) unit. Thus, the proposed extensions are simple to integrate into standard 32-bit RISC cores like the MIPS32 4Km. We present an optimized Assembly routine for fast multiple-precision multiplication with "finely" integrated Montgomery reduction (FIGS method). Simulation results demonstrate that the custom instructions double the processor's arithmetic performance compared to a standard MIPS32 core.
引用
收藏
页码:253 / 270
页数:18
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