Gate-all-around poly-Si nanowire junctionless thin-film transistors with multiple channels

被引：3

作者：

Tso, Chia-Tsung ^{[1
]}

Liu, Tung-Yu ^{[1
]}

Sheu, Jeng-Tzong ^{[1
]}

机构：

[1] Natl Chiao Tung Univ, Inst Nanotechnol, Dept Mat Sci & Engn, Hsinchu 30050, Taiwan

来源：

JAPANESE JOURNAL OF APPLIED PHYSICS | 2015年 / 54卷 / 06期

关键词：

MOSFETS; DESIGN; TFTS;

D O I：

10.7567/JJAP.54.06FG06

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

Polycrystalline silicon (poly-Si) nanowire (NW) junctionless (JL) thin-film transistors composed of gate-all-around (GAA) and multiple channels were demonstrated and characterized. The high surface-to-volume ratio of the NW and a nominal gate length of 0.25 mu m lead to a clear improvement in electrical performance, including a steep subthreshold swing (SS; similar to 124 mV/decade), a virtual absence of drain-induced barrier lowering (DIBL; 21 +/- 13 mV/V), and a high I-ON/I-OFF current ratio (similar to 1 x 10(9)) under a relatively low voltage condition (V-D = 0.3 V, V-G = 5 V), resulting from the multiple-channel structure and small grain boundaries and defects under the gate area. (C) 2015 The Japan Society of Applied Physics

引用

页数：3

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