Temperature Influence on the Electrical Properties of Vertically Stacked Nanowire MOSFETs

被引：0
|
作者：
Rodrigues, Jaime C. [1 ]
Mariniello, Genaro [1 ]
Casse, Mikael [2 ]
Barraud, Sylvain [2 ]
Vinet, Maud [2 ]
Faynot, Olivier [2 ]
Pavanello, Marcelo A. [1 ]
机构：
[1] Ctr Univ FEI, Dept Elect Engn, Sao Bernardo Do Campo, Brazil
[2] CEA Leti, Grenoble, France
来源：
35TH SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY AND DEVICES (SBMICRO2021) | 2021年
基金：
巴西圣保罗研究基金会;
关键词：
Stacked Nanowires; Low temperature; Electrical characterization; transcondutance; threshold voltage; subthreshold slope; Multigate transistors;
D O I：
10.1109/SBMicro50945.2021.9585748
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper aims at analyzing the electrical characteristics of 2-level Stacked Nanowire MOSFETs at low temperatures. Fundamental device parameters such as threshold voltage, subthreshold slope and transconductance are evaluated in the temperature range of 160K to 400K. The influence of fin width variation is also studied. An analytical model of multiple-gate nanowire MOSFETs is employed to explain the experimentally observed data. It is demonstrated that the threshold voltage increases linearly with the temperature reduction. Stacked nanowires with wider fin width presents larger threshold variation with temperature.
引用
收藏
页数：4
相关论文
共 50 条
  • [1] Design and Optimization of 6T SRAM using Vertically Stacked Nanowire MOSFETs
    Tsai, Ming-Fu
    Fan, Ming-Long
    Pao, Chia-Hao
    Chen, Yin-Nien
    Hu, Vita Pi-Ho
    Su, Pin
    Chuang, Ching-Te
    [J]. 2013 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS (VLSI-TSA), 2013,
  • [2] Vertically Stacked and Independently Controlled Twin-Gate MOSFETs on a Single Si Nanowire
    Li, Xiang
    Chen, Zhixian
    Shen, Nansheng
    Sarkar, Deblina
    Singh, Navab
    Banerjee, Kaustav
    Lo, Guo-Qiang
    Kwong, Dim-Lee
    [J]. IEEE ELECTRON DEVICE LETTERS, 2011, 32 (11) : 1492 - 1494
  • [3] Methodology to separate channel conductions of two level vertically stacked SOI nanowire MOSFETs
    Paz, Bruna Cardoso
    Casse, Mikael
    Barraud, Sylvain
    Reimbold, Gilles
    Vinet, Maud
    Faynot, Olivier
    Pavanello, Marcelo Antonio
    [J]. SOLID-STATE ELECTRONICS, 2018, 149 : 62 - 70
  • [4] New method for individual electrical characterization of stacked SOI nanowire MOSFETs
    Paz, Bruna Cardoso
    Casse, Mikael
    Barraud, Sylvain
    Reimbold, Gilles
    Vinet, Maud
    Faynot, Olivier
    Pavanello, Marcelo Antonio
    [J]. 2017 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S), 2017,
  • [5] Vertically Stacked Nanowire MOSFETs for Sub-10 nm Nodes: Advanced Topography, Device, Variability, and Reliability Simulations
    Karner, M.
    Baumgartner, O.
    Stanojevic, Z.
    Schanovsky, F.
    Strof, G.
    Kernstock, C.
    Karner, H. W.
    Rzepa, G.
    Grasser, T.
    [J]. 2016 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2016,
  • [6] Vertically Stacked Silicon Nanowire Photodetectors for Spectral Reconstruction
    Meng, Jiajun
    Cadusch, Jasper J.
    Crozier, Kenneth B.
    [J]. 2019 CONFERENCE ON LASERS AND ELECTRO-OPTICS (CLEO), 2019,
  • [7] Investigation and optimization of electrical and thermal performance for 5-nm GAA vertically stacked nanowire FETs
    Huang, Ning
    Liu, Weijing
    Li, Qinghua
    Bai, Wei
    Tang, Xiadong
    Yang, Ting
    [J]. MICROELECTRONICS JOURNAL, 2020, 95
  • [8] Investigation of Self-Heating Effects in Gate-All-Around MOSFETs With Vertically Stacked Multiple Silicon Nanowire Channels
    Park, Jun-Young
    Lee, Byung-Hyun
    Chang, Ki Soo
    Kim, Dong Uk
    Jeong, Chanbae
    Kim, Choong-Ki
    Bae, Hagyoul
    Choi, Yang-Kyu
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2017, 64 (11) : 4393 - 4399
  • [9] Investigation of the electrical properties of vertically stacked interface-treated Josephson junctions
    Yoshinaga, Y
    Izawa, S
    Wakita, K
    Ito, T
    Inoue, M
    Fujimaki, A
    Hayakawa, H
    [J]. SUPERCONDUCTOR SCIENCE & TECHNOLOGY, 2004, 17 (04): : 653 - 656
  • [10] Vertically stacked SiGe nanowire array channel CMOS transistors
    Fang, W. W.
    Singh, N.
    Bera, L. K.
    Nguyen, H. S.
    Rustagi, S. C.
    Lo, G. Q.
    Balasubramanian, N.
    Kwong, D. -L.
    [J]. IEEE ELECTRON DEVICE LETTERS, 2007, 28 (03) : 211 - 213
12345