Research on A Low Power Consumption for Single Input Change Test Theory

This paper presents a low-power test techniques for single input change. By adding simple control logic on Original synchronous counter of hexadecimal, the output of counter are modified, and single input change test sequences can be generated. The new single input change sequences optimize the switching activity of circuit-under-test, and then result in decrease of test power consumption. Initially, the design method bases of the generation of single input change test sequences are introduced. Then a test implementation for decoder integrated circuits is analyzed, The results show that Single Input Change test sequences are more effective than classical Multiple Input Change test sequences when a power test is targeted,67% of the switching activity is reduced and has no impact on the fault coverage, shows this scheme is practicality.